Senior Design Verification Engineer – SerDes IP

Role Overview

This position involves working with the SerDes IP team to focus on the verification of high-speed wireline transceivers, specifically working with technologies such as PAM4 at 56G/112G and beyond. The selected engineer will engage in the verification of complex SerDes digital and mixed-signal subsystems while collaborating closely with departments such as architecture, design, and circuit/modeling to ensure the system meets necessary specifications across various conditions.

Professional Experience Level

This role is suited for a candidate with extensive experience in design verification, expected to have approximately 5 or more years in the field.

Key Duties

The responsibilities of this position include ownership of the verification process for various SerDes digital IP blocks, development of verification plans with clear coverage goals, the building and maintenance of UVM environments, and supporting simulation acceleration efforts as necessary.

Job Requirements

Candidates must possess strong hands-on experience with SystemVerilog and UVM, along with a solid understanding of verification fundamentals. Proficiency in debugging and strong programming skills in either C/C++ or Python are also essential.

Education Requirements

A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field is required.