Senior Design Verification Engineer (DFT-DV)

Role Summary

This role focuses on verifying new and existing features for AMD's graphics processor IP, ensuring no bugs are present in the final design. Strong collaborative skills and a passion for processor architecture and digital design are essential.

Experience Level

Candidates should have a minimum of 7 years of experience in ASIC verification and debugging, with a strong proficiency in relevant technologies and languages.

Responsibilities

• Collaborate with architects and hardware engineers to understand new features for verification.
• Create block/chip-level Design Verification (DV) test plans.
• Develop UVM methodology-based verification testbenches from scratch.
• Create test cases and behavioral functional models.
• Understand Design-for-Test (DFT) and Design-for-Debug (DFD) architectures.
• Build directed and random verification tests.
• Debug test failures, collaborating with RTL engineers to resolve design defects.
• Ensure quality through regression testing and achieve 100% verification coverage.

Requirements

• Proficiency in IP level ASIC verification and debugging of firmware, as well as RTL code.
• Experience in UVM testbenches and simulation environments (Linux and Windows).
• Strong skills in Verilog, System Verilog, C, and C++.
• Experience developing UVM-based verification frameworks.
• Familiarity with scripting languages such as Perl, Ruby, Makefile, and shell.
• Leadership or mentorship experience is a plus.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required.