Senior Design Verification Engineer - DDR

Role Summary

The Senior Design Verification Engineer for DDR will lead technical teams to ensure the successful verification of high-performance silicon chips. This role involves working with cross-functional teams to achieve thorough verification coverage of IP cores.

Experience Level

3+ years in ASIC verification, with demonstrated leadership experience in DDR IP projects.

Responsibilities

• Lead and own critical areas of verification, collaborating with verification engineers.
• Design and implement advanced verification environments for synthesizable IP cores.
• Perform verification tasks ensuring functional correctness and high-quality deliverables.
• Develop and execute comprehensive test plans and environments at unit and system levels.
• Code and debug complex test cases, including checkers and assertions using System Verilog/UVM.
• Extract and review verification metrics to ensure quality standards are met.
• Manage regressions and analyze results to improve verification strategies.

Requirements

• BS/MS in Electrical Engineering or Electronics and Communication Engineering.
• Proven experience in leading teams for DDR IP projects.
• Expertise in developing HVL based test environments using System Verilog/UVM.
• Ability to create and execute rigorous test plans and assertions.
• Experience in extracting and analyzing verification metrics.
• Hands-on experience with end-to-end verification deliverables.

Education Requirements

BS/MS in Electrical Engineering or Electronics and Communication Engineering.