Senior Design Verification Engineer

Role Summary

The Senior Design Verification Engineer will be responsible for verifying design specifications and ensuring the functional correctness of complex digital designs. This includes developing test plans, writing and executing test cases, and creating simulation models.

Experience Level

This position is targeted for candidates with significant experience in design verification, typically requiring several years in a relevant field alongside a focused knowledge of hardware programming and verification tools.

Responsibilities

The core responsibilities of this role include:

• Developing and implementing verification methodologies.
• Performing thorough verification of digital designs.
• Debugging assertion failures and optimizing verification processes.
• Collaborating with design engineers to understand designs and create effective verification plans.
• Documenting verification activities and results for future reference.

Requirements

Applicants must meet the following requirements:

• Experience in SystemVerilog or similar languages.
• Strong background in digital design principles.
• Familiarity with verification tools such as UVM.
• Excellent problem-solving skills and attention to detail.
• Ability to work independently and as part of a team.

Education Requirements

A degree in Electrical Engineering, Computer Engineering, or a related discipline is required; advanced degrees are preferred.