Senior Design-for-Test Engineer

Role Summary

The Senior Design-for-Test Engineer role focuses on enhancing the design and implementation of test systems for semiconductor IP. You will be responsible for DFT tasks at the IP level and will collaborate closely with design teams to improve testability and quality.

Experience Level

This position requires a minimum of 2 years of relevant experience in DFT design, preferably within the semiconductor industry.

Responsibilities

Your primary responsibilities will include:

• Managing DFT tasks including scan chain stitching, ATPG, and simulation.
• Creating timing constraints for both mission and DFT modes.
• Collaborating with design and physical implementation teams on synthesis and constraint validation.
• Providing support for customer IP integration and silicon bring-up.
• Leading and coaching team members in DFT practices.

Requirements

The ideal candidate will possess:

• A BS, MS, or PhD in Electronics or a related field.
• At least 2 years of DFT design experience.
• Proficiency in scan insertion, ATPG, and JTAG methodologies.
• Familiarity with Synopsys tools such as Design Compiler, VCS, and TetraMAX is advantageous.
• Solid scripting abilities in languages such as Perl, TCL, or Python.

Education Requirements

Applicants should have at least a bachelor's degree in Electronics or a related discipline.