Role Summary
This position provides an opportunity to work with a custom standard cell design engineering team focusing on advanced technologies in deep submicron circuit design.
Experience Level
5+ years of relevant circuit design experience if holding a BSEE, or 4+ years with an MSEE.
Responsibilities
- Develop Arm custom standard cells in sub-3nm process technology nodes.
- Collaborate closely with physical design engineers to optimize PPA of Arm cores in SoCs.
- Work with the mask design team for layout tuning, characterization, and validation through QA processes using various EDA tools.
Requirements
- Significant experience in the identification, design, and verification of cells for improving PPA.
- Strong understanding of MOSFET electrical characteristics and layout variability at 3nm and below.
- Proven expertise in static circuit design including latches and flops.
- Experience with standard cell EDA view characterization and Spice circuit simulators.
- Proficient in scripting languages such as Perl or Python.
- Able to support the development of others and iteratively improve design solutions based on data analysis.
Education Requirements
BSEE or MSEE is required.