Senior Design Engineer – AI SoC Development

Role Summary

As a Senior Design Engineer in AI SoC Development at Intel, you will be responsible for developing logic design, register transfer level (RTL) coding, and simulation for SoC designs. This includes integrating IP blocks and subsystems into full chip SoC or discrete component designs.

Experience Level

Minimum of 7 years of experience in RTL design and implementation for ASIC/SoC development.

Responsibilities

• Lead evaluation of architectural trade-offs considering performance targets, power constraints, and system limitations.
• Define and document micro-architecture for complex SoC IP blocks; implement RTL in Verilog/SystemVerilog.
• Collaborate closely with verification teams to ensure comprehensive coverage and robust validation.
• Develop and maintain timing constraints for IP blocks; support physical design teams.
• Drive silicon bring-up and post-silicon validation, including debug and performance analysis.
• Mentor junior engineers and contribute to best practices for design methodology and quality.

Requirements

Minimum qualifications include a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.

Preferred qualifications include experience in complex design challenges, hands-on SoC integration, knowledge of standard bus protocols, high-speed and low-power design techniques, and proficiency in scripting for automation.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.