Senior Custom SOC IP Verification Engineer

Job Title

Senior Custom SOC IP Verification Engineer

Role Summary

Verify ASIC IP and full SOC designs for NVIDIA NVLink Fusion semi-custom silicon. The role focuses on developing verification environments, reference models, and methodologies to achieve coverage-driven sign-off.

Work closely with Architecture, Software/Firmware, Design, and Modeling teams to define verification plans and resolve silicon and platform issues.

Experience Level

Senior — requires 5+ years of experience owning processing ASIC, IP, or SoC design verification.

Responsibilities

Primary responsibilities include IP- and SOC-level verification, reference model development, testbench creation, and cross-team verification coordination.

• Lead ASIC design verification for IPs and SOCs.
• Develop and integrate reference models.
• Participate in architecture and micro-architecture reviews to define verification plans with Architecture, SW/FW, Design, and Modeling.
• Develop and improve verification methodologies; drive functional and code coverage to closure.
• Create complex testbenches and implement directed and constrained-random tests.
• Contribute to silicon and platform verification strategy and methodology.
• Triage SOC-level failures with SOCV/EMU and software teams.
• Collaborate with IP development teams and support IP identification, selection, and licensing processes.

Requirements

Must-have technical skills and experience to perform the role; listed nice-to-have items afterward.

• Must: Familiarity with industry verification tools such as Synopsys VCS or Cadence Xcelium, and debug/analysis tools like Verdi; experience with formal tools (JasperGold or VC Formal).
• Must: Proven track record of first-pass success in ASIC development and 5+ years owning ASIC/IP/SoC verification.
• Must: Experience developing and delivering complex mixed-language UVM and C++ testbenches.
• Must: Ability to interpret functional specifications and produce comprehensive test plans.
• Must: Ability to write directed and constrained-random tests for coverage-driven closure.
• Must: Strong programming skills in C++ and SystemC; familiar with GDB for debugging.
• Must: Experience developing tools and infrastructure using Perl or Python.
• Must: Experience managing multiple projects and adjusting priorities with stakeholders.
• Nice-to-have: Hands-on experience with AMBA protocols (AXI, ACE, CHI).
• Nice-to-have: Experience with complex subsystems such as ARM CPU complexes, LPDDR, HBM, GPUs, UCIE, PCIe, or NoC and performance verification.

Education Requirements

B.S. or M.S. degree in Computer Engineering or Electrical Engineering.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.