Senior CPU RTL Design Engineer – Power Management
Intel CorporationJob Title
Senior CPU RTL Design Engineer – Power Management
Role Summary
Senior engineer on the CPU Design team responsible for designing power-aware CPU microarchitecture and delivering RTL for CPU IP blocks. The role partners with architecture, verification, physical design, and SoC integration teams to optimize power, performance, and area for shipping silicon.
Experience Level
Senior-level. See the Education Requirements section for degree and years-of-experience guidance.
Responsibilities
Primary technical responsibilities include:
- Define, design, and implement CPU microarchitecture features.
- Develop and deliver RTL (SystemVerilog/Verilog) for CPU IP blocks.
- Drive power, performance, and area (PPA) optimization with emphasis on power-aware RTL and energy-efficient architectures.
- Design and validate multi-clock domain solutions and clock domain crossing (CDC) techniques.
- Design and validate CPU power management features (DVFS, power/thermal management, reset flows, power-state transitions).
- Debug complex RTL and collaborate closely with verification teams.
- Partner with SoC integration teams for full-chip delivery and handoff to physical design.
- Contribute to design methodology improvements and scalability.
Requirements
Must-have technical skills and experience (minimum qualifications are summarized without degree details below; see Education Requirements for degree/years specifics):
- Hands-on experience with power management concepts such as DVFS, power states, and budgeting.
- Practical experience in low-power / power-aware CPU or SoC RTL design.
- RTL development using Verilog/SystemVerilog and strong RTL debugging capability.
- System-level design understanding and ability to collaborate with verification and integration teams.
- Focus on PPA optimization in RTL and architecture.
Nice-to-have:
- Experience with multi-clock domain / CDC design and validation.
- Familiarity with CPU ISAs and system architecture (e.g., x86) and assembly language.
- Experience with high-speed datapath/circuits, timing convergence, static timing analysis, UPF, and lint flows.
Education Requirements
Minimum qualifications specify a Bachelor's degree in Electrical/Computer Engineering, Computer Science, or a related field with 9+ years of relevant experience, or a Master's degree in those fields with 7+ years of relevant experience. Fields called out include Electrical/Computer Engineering and Computer Science.
About the Company
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
