Senior Clock Architecture & Design Engineer
Intel CorporationJob Title
Senior Clock Architecture & Design Engineer
Role Summary
Responsible for architecting and implementing clock distribution and custom clock circuits for flagship, high-frequency CPU designs. Works with architecture, physical design, validation, and EDA partners to deliver clocking solutions on advanced process nodes.
The role focuses on clock tree synthesis flows, transistor-level custom design, timing closure, and cross-team technical leadership to meet performance and power targets.
Experience Level
Senior. Typical experience guidance: industry experience in relevant roles (see Education Requirements for degree/experience equivalencies).
Responsibilities
Key responsibilities include designing and delivering clocking solutions for high-performance CPU projects.
- Architect and implement clock distribution networks and custom clock solutions for high-frequency CPU designs.
- Design transistor-level custom circuits and library cells to meet performance and power targets; perform SPICE simulations and circuit characterization.
- Develop and optimize advanced clock tree synthesis (CTS) flows for complex, full-chip designs.
- Collaborate with architecture, physical design, validation, and EDA teams to integrate clock solutions into the design flow.
- Interface with EDA vendors to influence and adapt design automation tools for clocking needs.
- Drive timing closure efforts related to clocking; participate in constraint development and timing verification.
- Provide technical guidance and mentorship within project teams and take ownership through implementation and signoff.
Requirements
Must-have technical skills and experience. Preferred items listed separately.
- Experience in physical design flows, clock tree synthesis (CTS), and static timing analysis.
- Strong background in custom circuit design, transistor-level design, and SPICE simulations.
- Proficiency in programming and scripting (industry-standard scripting languages) for automation and flow development.
- Experience with full-chip design tools and timing closure methodologies (preferred as nice-to-have where noted).
Nice-to-have:
- Hands-on experience designing high-frequency custom clock networks on leading-edge nodes.
- Experience with clocking architecture and PLL/DLL design and integration.
- Expertise in timing constraint adaptation and large-scale timing closure methods.
Education Requirements
Degree and experience equivalencies: Bachelor's degree in Electrical Engineering, Computer Engineering or related STEM field (with 5+ years relevant experience), OR Master's in a related field (with 3+ years), OR PhD in a related field (with 1+ year). Related technical fields and equivalent practical experience are accepted.
About the Company
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
