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Senior ASIC/VLSI Design Engineer — RTL / Verilog / SystemVerilog

Macpower Digital Assets Edge
June 23, 2026
Full-time
On-site
Austin, Texas, United States
$160,000 - $180,000 USD yearly
RTL Design Jobs, Level - Senior

Job Title

Senior ASIC/VLSI Design Engineer — RTL / Verilog / SystemVerilog

Role Summary

Senior ASIC/VLSI engineer joining a core design team in Austin, TX to implement RTL for next-generation DSP and communication SoCs focused on high-speed, low-power AI and cloud connectivity. Role is onsite, five days per week.

H‑1B sponsorship available. Competitive base salary, equity, and medical/dental benefits were advertised.

Experience Level

Senior — typically requires 5+ years of ASIC/VLSI digital design experience (as stated in the posting).

Responsibilities

The engineer will translate algorithms into efficient hardware, implement and optimize RTL, and collaborate across design, verification, DFT, and backend teams.

  • Define micro-architecture and write synthesis-friendly RTL in Verilog/SystemVerilog.
  • Perform synthesis, timing analysis, and PPA optimization (power, performance, area).
  • Collaborate with verification, DFT, and backend teams; participate in design reviews and defend architectural decisions.
  • Support IP/SoC integration and produce interface documentation.
  • Debug pre- and post-silicon issues using simulation, waveform analysis, and lab bring-up.
  • Contribute to design methodology, tooling, and process improvements.

Requirements

Key technical and practical requirements for the role.

  • 5+ years of ASIC/VLSI digital design engineering experience.
  • Proficiency in Verilog and SystemVerilog for RTL design.
  • Solid understanding of the ASIC design flow: synthesis, linting, CDC, and SDC constraints.
  • Experience with DFT (scan insertion, ATPG, BIST).
  • Strong debugging and analytical skills for simulation and silicon bring-up.
  • Experience with IP/SoC integration and system-level interfaces.

Nice to have:

  • Experience with optical communication systems or high-speed Ethernet (100G+).
  • Background in DSP-oriented hardware blocks.
  • Scripting skills (Python, Perl, or TCL).
  • Startup experience and ability to work independently in a fast-paced environment.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering or Computer Engineering is specified.


About the Company

Company: Macpower Digital Assets Edge

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Date Posted: 2026-06-19