Senior ASIC Verification Engineer

Job Title

Senior ASIC Verification Engineer

Role Summary

Join a digital hardware team as a senior verification engineer working remotely across the full silicon development lifecycle: micro-architecture definition, RTL verification, ASIC/FPGA/SoC implementation, and on-hardware bring-up. The role requires technical ownership of verification deliverables and frequent collaboration with architecture, RTL, firmware, and software teams.

Experience Level

Senior-level (title specifies Senior). Typical experience for this level is 7+ years, though no explicit years requirement was listed.

Responsibilities

Primary responsibilities include planning and executing functional verification for high-performance compute subsystems and driving sign-off-quality verification closure.

• Develop UVM/SystemVerilog testbenches and verification IP for subsystems such as systolic arrays, vector/tensor datapaths, DMA engines, memory hierarchies, and control logic.
• Define verification plans, test strategies, and coverage goals (functional, code, assertion) and drive closure to sign-off criteria.
• Build constrained-random and directed tests to validate ML datapath correctness (GEMM, convolutions, attention, mixed-precision arithmetic).
• Verify power-management behavior including clock/operand gating, power islands, DVFS transitions, and idle/wake sequences in coordination with firmware policies.
• Create and maintain SVA assertions, scoreboards, reference models, and protocol/datapath checkers (AXI/CHI/NOC, DMA, memory interfaces).
• Run block- and SoC-level simulation regressions; debug failures using waveforms, logs, and cross-team RTL reviews.
• Partner with RTL, architecture, firmware, and software teams for hardware-software co-verification and early emulation/FPGA bring-up.
• Contribute to low-power verification methodology and correlate pre-silicon models with post-silicon power measurements.

Requirements

Required technical skills and experience for immediate contribution.

• Proven experience developing UVM/SystemVerilog testbenches, verification IP, scoreboards, and checkers.
• Strong understanding of digital electronics, logic design, and ASIC/FPGA/SoC fundamentals.
• Experience taking designs through the full lifecycle on real hardware (FPGA, SoC, or ASIC) and performing on-hardware bring-up/debug.
• Familiarity with verification methodology: constrained-random testing, coverage-driven verification, and assertion-based verification (SVA).
• Experience debugging simulation failures using waveforms and logs and collaborating in cross-functional RTL reviews.
• Knowledge of common on-chip protocols and interfaces (AXI/CHI/NOC, DMA, memory interfaces).
• Customer-facing communication: presenting technical solutions, gathering requirements, and supporting PoC and production phases.

Education Requirements

BSc or MSc in Electronics, Radio Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Oso Semiconductor

Headquarters: Mountain View, CA, United States

Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2–4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.