Senior ASIC RTL Design Engineer

Role Overview

The Senior ASIC RTL Design Engineer will be responsible for creating advanced digital designs and developing various IPs for System on Chip (SoC). This role involves close collaboration with various teams including architecture, physical design, and product engineers to achieve successful silicon outcomes.

Position Summary

This position requires a strong foundation in modern processor architecture and digital design, as well as verification and design quality assurance. The ideal candidate should excel in teamwork and possess excellent analytical and problem-solving abilities, with an eagerness to tackle challenges in a multi-site environment.

Experience Level

This role is suited for experienced professionals who have a strong background in ASIC design and RTL development with a proven track record of success in complex projects.

Core Responsibilities

• Design RTL for high-speed circuits with features such as clock reset and power management.
• Optimize designs for power efficiency and implement low power design techniques.
• Resolve integration issues between various IP components.
• Oversee clock-domain crossing and linting aspects of the overall design.
• Collaborate with cross-functional teams to incorporate feedback into designs.
• Document design features through thorough architectural specifications.
• Demonstrate a commitment to teamwork through effective communication and documentation practices.

Qualifications

The successful candidate should possess extensive experience in digital IP/ASIC design, Verilog RTL, and a thorough understanding of the complete IP design cycle, including verification and timing closure. Familiarity with low power design is advantageous, along with programming skills in scripting languages such as Python or Perl. Strong leadership, organizational, and multitasking skills are also essential.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.