Senior ASIC RTL Design Engineer, AI Hardware
CerebrasJob Title
Senior ASIC RTL Design Engineer, AI Hardware
Role Summary
Senior front-end ASIC engineer on the Wafer Scale Engine (WSE) hardware team. The role focuses on RTL design, microarchitecture, and integration to deliver high-performance, power-efficient, and scalable AI accelerator silicon.
You will collaborate with physical design, verification, DFT, software and systems teams to take architectures from specification through silicon bring-up.
Experience Level
Senior - typically 8+ years of relevant ASIC/RTL experience; demonstrated track record of multiple silicon tape-outs.
Responsibilities
Contribute across front-end chip design and deliver RTL into silicon while coordinating with cross-functional teams.
- Define functional specifications and micro-architecture for new blocks.
- Develop and integrate RTL; own synthesis and design-for-test considerations.
- Collaborate with physical design to meet performance, power, and area (PPA) targets.
- Work with verification and DFT teams to achieve coverage and quality goals.
- Integrate third-party IP and manage front-end chip integration tasks.
- Debug silicon-level functional, timing, and power issues during bring-up.
- Coordinate with software and system teams to optimize performance and features.
- Engage with external vendors as required through the development cycle.
Requirements
Must-have technical skills and experience for this role.
- 8+ years delivering complex, high-performance RTL designs for ASICs.
- Front-end chip integration experience and third-party IP integration.
- Experience in high-performance computing, GPU/CPU designs, machine learning or closely related domains.
- Proven history of multiple silicon successes and silicon bring-up experience.
- Experience collaborating with external vendors and cross-functional teams.
- Networking stack experience, such as TCP/IP, RDMA, and Ethernet.
- Familiarity with PCIe, CPU interfaces, and SerDes technologies.
- Scripting proficiency: Python and TCL.
- Ability to work in a hybrid environment and participate in on-site activities as needed.
- Nice-to-have: FPGA toolchain knowledge, place-and-route, floorplanning, timing analysis, and vendor management through ASIC cycles.
Education Requirements
Master's degree in Computer Science, Electrical Engineering, or a related technical field preferred; equivalent practical experience accepted.
About the Company
Company: Cerebras
Headquarters: Sunnyvale, CA, USA
Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)-one of the world’s largest AI chips-to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.
