Senior ASIC Physical Design Technical Lead
Cisco SystemsJob Title
Senior ASIC Physical Design Technical Lead
Role Summary
Join Cisco's Common Hardware Group (CHG) as a senior physical-design technical lead responsible for full-chip floorplanning and RTL-to-GDSII implementation for advanced networking ASICs. The role partners with architecture, package, RTL, DFT, implementation teams and EDA/foundry vendors to deliver high-quality designs and improve design methodology.
Experience Level
Senior — see Education Requirements for specific experience-by-degree guidance (typical range: 5+ to 12+ years of physical-design experience).
Responsibilities
Primary responsibilities include full-chip implementation, cross-team coordination, and methodology improvements.
- Define and implement full-chip floorplans considering architecture and IP placement constraints.
- Coordinate requirements with system and package design teams and incorporate them into the floorplan.
- Perform hierarchical implementation flows: partitioning, pin assignment, and clock planning.
- Execute RTL-to-GDSII implementation with focus on timing, power, and die-size optimization.
- Analyze and improve EDA tool flows and physical-design methodologies to increase efficiency.
- Work with RTL, DFT, implementation teams and EDA/foundry/IP vendors to enable robust signoff-ready flows.
- Apply low-power design techniques and collaborate with foundry/IP teams on signoff methodologies.
Requirements
Must-have technical skills and domain experience.
- Extensive hands-on experience with full-chip activities and RTL-to-GDSII flows in advanced process nodes (examples: 7nm, 5nm, 3nm).
- Proficiency with physical-design and signoff EDA tools such as Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre/Pegasus.
- Experience with hierarchical design, timing closure, static timing analysis, and defining timing constraints.
- Expertise in full-chip floorplanning, power-grid planning and power-integrity analysis.
- Familiarity with chip-level/custom clock design and clock planning techniques.
- Proficiency in scripting (Python) and practical use of AI tools or automation to improve productivity.
- Proven ability to work cross-functionally and coordinate with EDA and foundry partners.
Education Requirements
Bachelor's degree in Electrical Engineering with 12+ years of physical-design experience; or Master's degree with 8+ years; or PhD with 5+ years. Degree listed in posting: Electrical Engineering. (No other degrees, fields, certifications, or explicit equivalent-experience language were provided.)
About the Company
Company: Cisco Systems
Headquarters: San Jose, CA, United States
Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).
