Senior ASIC Physical Design Engineering Technical Lead

Job Title

Senior ASIC Physical Design Engineering Technical Lead

Role Summary

Lead and execute full-chip physical implementation for advanced ASICs within the Common Hardware Group, collaborating with RTL, package, system, foundry, IP vendors and EDA teams. Focus on floorplanning, hierarchical implementation, timing closure, power integrity, and die-size optimization for high-performance silicon.

Experience Level

Senior-level. Role requires extensive physical-design leadership and hands-on implementation experience; specific experience guidance varies by degree (see Education Requirements).

Responsibilities

Primary responsibilities focus on end-to-end physical implementation and improving design flows and methodologies.

• Create and validate full-chip floorplans considering architecture, foundry guidelines, and IP placement constraints.
• Collaborate with system and package teams to incorporate package and system requirements into the floorplan.
• Execute hierarchical implementation: partitioning, pin assignment, clock planning, bump planning, and hierarchy management.
• Implement RTL-to-GDSII flow: floorplan, power-grid planning, place-and-route, static timing analysis, power integrity, physical verification and equivalence checks.
• Design and verify custom chip-level clock strategies (mesh and H-tree) and optimize for timing, power, and die size.
• Analyze existing tool flows and methodologies; identify gaps and implement incremental or transformative improvements.
• Work closely with RTL, DFT, EDA vendors, tool/flow teams, foundry and IP partners to define and validate signoff methodologies and post-silicon feedback loops.
• Leverage automation and AI tools to improve productivity and repeatability.

Requirements

Must-have and preferred technical skills and domain experience relevant to advanced-node full-chip physical design.

Must-have:

• Extensive hands-on physical-design experience including RTL-to-GDSII implementation and design tapeouts at advanced process nodes (7nm / 5nm / 3nm or below).
• Experience with commercial EDA tools such as Innovus, Tempus/PrimeTime, RedHawk/Voltus, and Calibre/Pegasus.
• Proven experience in floorplanning, power-grid planning, place-and-route, static timing analysis and physical verification for performance- and power-sensitive designs.
• Practical knowledge of low-power design methodologies and use of UPF in implementation flows.
• Ability to collaborate effectively with foundry and IP vendors and to translate post-silicon validation feedback into signoff adjustments.

Nice-to-have:

• Experience with hierarchical design flows, timing closure at chip level, and physical design convergence techniques.
• Hands-on experience with custom chip clock architectures (H-tree, mesh) and full-chip clock mesh/Flex-HTree methods.
• Experience with Python for flow automation and demonstrated use of AI tools (prompting and integration) to improve productivity.

Education Requirements

Degree and experience combinations listed in the posting: Bachelor's degree in Electrical Engineering with 12+ years of physical-design experience; Master’s degree in Electrical Engineering with 8+ years; or PhD in Electrical Engineering with 5+ years. The posting allows equivalent practical experience in lieu of the listed degree/years.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).