Senior ASIC Physical Design Engineer (Security Clearance Required)

Job Title

Senior ASIC Physical Design Engineer (Security Clearance Required)

Role Summary

The Senior ASIC Physical Design Engineer will lead digital back-end implementation for custom ASICs, driving synthesis, floorplanning, timing closure, physical verification, and tapeout readiness. The role sits within a miniature device technologies team that develops custom ASIC, PCB, FPGA, and embedded solutions for national security applications.

Work includes process selection, custom physical layout when needed, tool and environment improvements, and mentoring junior engineers while collaborating with digital design, verification, and software teams.

Experience Level

Senior — requires at least 6 years of back-end ASIC design experience (posting specifies 6+ years).

Responsibilities

Primary responsibilities focus on digital back-end flow, physical verification, and cross-functional delivery of production-ready ASIC layouts.

• Implement full digital back-end flow from synthesis to a verified top-level layout ready for tapeout.
• Floorplan top-level digital and mixed-signal ASIC layouts and perform partitioning to meet timing and area goals.
• Perform timing analysis and timing closure; identify and resolve RTL- and gate-level back-end issues with digital designers.
• Insert SCAN and BIST for defect coverage and support testability.
• Execute physical verification workflows (DRC, DRC+, MCD, LVS) using industry tools.
• Perform custom physical layout and top-level modifications as required.
• Assess process options for new designs, including size, power, required features, and available IP.
• Enhance ASIC design environment and scripting to improve productivity and quality.
• Provide technical leadership, mentor junior physical design engineers, and maintain cross-team communication.

Requirements

Must-have technical skills, experience, and eligibility.

• 6+ years of hands-on back-end ASIC physical design experience.
• Proficient with Cadence back-end tools for synthesis, placement, and routing.
• Proficient with Siemens Calibre or equivalent physical verification tools for DRC/LVS/MCD.
• Proven experience with timing analysis, floorplanning, SCAN/BIST insertion, and physical verification signoff.
• Ability to obtain an Interim Secret security clearance by start date and ultimately obtain a Secret clearance; eligibility requires U.S. citizenship.

Nice-to-have:

• Experience with Cadence Virtuoso for custom layout.
• Experience using Siemens (Mentor) ASIC back-end toolchains.
• Experience in ASIC technology characterization and process selection.
• Active security clearance or prior single-scope background investigation.

Education Requirements

Possess an Associate's degree in a technical field, or equivalent combination of education, experience, and certifications (posting explicitly allows equivalent practical experience in place of a degree).

About the Company

Company: Johns Hopkins Applied Physics Laboratory

Headquarters: Laurel, Maryland, United States

Johns Hopkins Applied Physics Laboratory is a nonprofit, university-affiliated research center that develops advanced engineering, science, and technology solutions for national security, space, and government-sponsored missions.