Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
Responsible for physical design implementation of CPU on-chip interconnect networks and last-level caches. Work includes synthesis, timing closure, floorplanning and collaborating with logic and micro-architecture teams to meet area, performance and power targets.
This role is on NVIDIA's CPU Cache Coherent Interconnects team and contributes to high-performance semiconductor products across the company.
Senior β typically 5+ years of experience in processor or other high-performance semiconductor design.
Core responsibilities include implementation and optimization of on-chip interconnects and caches, driving timing closure, and collaborating across teams.
Must-have technical skills and relevant experience; preferred items listed where applicable.
Masters degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent practical experience.
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
