Senior ASIC Physical Design Engineer

Job Title

Senior ASIC Physical Design Engineer

Role Summary

Senior physical-design engineer responsible for digital back-end flow for ASICs within the Miniature Device Technologies Group. Deliver tapeout-ready top-level layouts by owning synthesis, floor-planning, timing closure, verification, and custom physical layout.

Work with digital design, verification, and software teams to identify and resolve back-end issues, select processes for new designs, and mentor junior engineers on physical design practices for low-power miniature systems supporting national-security missions.

Experience Level

Senior-level. Requires 6+ years of experience performing back-end ASIC design.

Responsibilities

Primary responsibilities include delivering complete, verified top-level ASIC layouts and supporting the team across back-end activities:

• Implement full digital back-end flow from synthesis through layout and tapeout submission.
• Top-level floorplanning for digital and mixed-signal ASICs and design partitioning to meet timing.
• Perform timing analysis and closure; debug RTL and gate-level issues related to back-end implementation.
• Insert SCAN and BIST to maximize defect coverage.
• Execute physical verification (DRC, DRC+, MCD, LVS) and resolve violations.
• Perform custom physical layout and top-level custom modifications as needed.
• Contribute to environment enhancements and scripting to improve design flows.
• Provide technical leadership and mentorship to junior physical-design engineers and collaborate with cross-functional teams to meet project goals.

Requirements

Key qualifications and security requirements.

Must-have

• 6+ years of hands-on back-end ASIC design experience.
• Proficiency with Cadence ASIC back-end design tools.
• Experience using Siemens Calibre for physical verification.
• Ability to obtain an Interim Secret security clearance by start date and ultimately a Secret clearance; eligibility requires U.S. citizenship.

Nice-to-have

• Experience with custom physical layout in Cadence Virtuoso.
• Familiarity with Siemens ASIC back-end toolsets beyond Calibre.
• Experience in ASIC technology characterization and process selection.
• Active security clearance or prior single-scope background investigation.

Education Requirements

Associate's degree in a technical field preferred, or an equivalent combination of education, experience, and/or certifications.

About the Company

Company: Johns Hopkins Applied Physics Laboratory

Headquarters: Laurel, Maryland, United States

Johns Hopkins Applied Physics Laboratory is a nonprofit, university-affiliated research center that develops advanced engineering, science, and technology solutions for national security, space, and government-sponsored missions.