Senior ASIC Physical Design Engineer

Job Title

Senior ASIC Physical Design Engineer

Role Summary

Lead development of front-end physical design workflows and implementations for generative AI inference ASICs. Work within the ASIC engineering team to optimize block- and full-chip frontend flows, STA, power analysis, and EDA tool usage to deliver high-performance, low-power SoCs.

Experience Level

Senior - 10+ years of hands-on ASIC engineering experience (as stated in the posting).

Responsibilities

Primary responsibilities include ownership and improvement of frontend physical design flows and collaboration with cross-functional ASIC teams.

• Lead front-end physical design and engineering workflow development for generative AI inference products.
• Guide and coach engineers to improve frontend physical design at block and full-chip levels.
• Drive optimization and implementation of synthesis, formal checks, power analysis, and related frontend workflows.
• Provide guidance on static timing analysis (STA) and constraints for block and full-chip timing closure.
• Develop scalable, reliable tools and automation to improve EDA workflows and engineering productivity.
• Collaborate closely with ASIC team members to understand and address their EDA and workflow requirements.

Requirements

Summary of must-have technical skills followed by a few desirable items.

• Must-have: 10+ years hands-on ASIC engineering experience with deep knowledge of VLSI/SoC physical design workflows.
• Must-have: Experience with EDA tools such as Cadence or Synopsys (e.g., Genus/DC), synthesis, power analysis, and clock methodology.
• Must-have: Strong front-end physical design expertise for block- and full-chip optimization and implementation.
• Must-have: Proficiency with static timing analysis (STA), timing constraints, and timing closure practices.
• Must-have: Strong analytical, written, and verbal communication skills; ability to collaborate across a global engineering team.
• Nice-to-have: Experience leading backend design tasks or teams with familiarity of clock trees, routing, DRC/LVS, metal fill, and artwork release.

Education Requirements

Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field - or equivalent practical experience.

About the Company

Company: Tensordyne

Tensordyne is a startup developing high-performance, low-power AI inference processors and multi-chip systems for generative AI acceleration in data centers. The company focuses on ASIC design, verification, and integration of computational accelerators with third-party SoC IP.