Senior ASIC Digital Design Engineer

Role Summary

The Senior ASIC Digital Design Engineer will lead the design and development of complex ASIC digital subsystems. This role focuses on crafting robust architectures, ensuring high-quality implementation, and mentoring junior engineers in a collaborative team environment.

Experience Level

Minimum of 8 years of hands-on experience in RTL design and ASIC/SoC subsystem architecture, including extensive work with industry-standard protocols.

Responsibilities

• Lead the complete lifecycle of digital subsystem design, from initial requirements to final release.
• Develop subsystem architectures and comprehensive functional specifications.
• Define and ensure adherence to best RTL coding practices and micro-architectures.
• Conduct rigorous RTL quality checks and verify bug-free delivery.
• Collaborate with verification, DFT, and physical implementation teams for project success.
• Integrate standard protocols such as PCIe, DDR, UFS, USB, and AMBA within subsystem designs.
• Apply low power design methodologies and ensure compliance with DFT requirements.
• Mentor junior team members and participate in technical reviews.

Requirements

• Proficiency in RTL design using Verilog/SystemVerilog and familiarity with verification tools.
• Experience with standard protocols including PCIe, DDR, UFS, USB, and AMBA.
• Strong understanding of ASIC design flow including synthesis and timing analysis.
• Ability to lead cross-functional collaborations throughout project phases.
• Exceptional communication and leadership skills conducive to a multicultural team environment.

Education Requirements

While specific degree requirements are not stated, a degree in Electrical Engineering or related fields is typically expected for this level of position.