Senior ASIC Digital Design Engineer
SynopsysJob Title
Senior ASIC Digital Design Engineer
Role Summary
Senior RTL engineer on the PCIe controller IP team responsible for implementing, debugging, and owning complex PCIe (or equivalent high-speed interface) blocks from micro-architecture and design specs through silicon delivery. Work closely with verification, physical design, and senior engineering leadership to deliver production-quality, maintainable RTL.
Experience Level
Senior - typically 5+ years of relevant ASIC digital design experience.
Responsibilities
Primary ownership and delivery of RTL features for PCIe IP and related subsystems, including design, debug, and cross-team collaboration.
- Implement and own RTL for PCIe blocks and features from micro-architecture and design specifications.
- Debug design issues using simulation and, when required, formal, emulation, or silicon bring-up support.
- Participate in micro-architecture reviews; document design intent and corner cases.
- Enforce RTL coding standards, lint and CDC hygiene, and drive review comments to closure.
- Collaborate with verification to define coverage, identify root causes, and deliver timely fixes.
- Support synthesis, timing, and low-power feedback from physical design for owned blocks.
- Mentor junior engineers and develop toward broader subsystem ownership.
Requirements
Must-have technical skills and experience for immediate impact; nice-to-have items listed separately.
- Must-have: Hands-on ASIC RTL design experience in SystemVerilog on production designs; strong understanding of clocks, resets, FSMs, pipelines, and synthesizable coding practices.
- Must-have: Experience with at least one high-speed interface or interconnect: PCIe, CXL, AMBA/AXI, DDR, Ethernet, or similar data-path/protocol work.
- Must-have: Practical simulation debug experience and ability to close issues with verification.
- Nice-to-have: Exposure to lint, CDC, synthesis, timing closure, formal methods, emulation, or silicon bring-up.
- Nice-to-have: Scripting skills (Python, TCL, Perl) and familiarity with AI-assisted design tools.
- Professional traits: Delivers high-quality, maintainable RTL; responsive in reviews and debugging; curious about protocols and micro-architecture.
Education Requirements
Bachelor of Science in Electrical Engineering (BSEE) with 5+ years relevant experience, or Master of Science in Electrical Engineering (MSEE) with 3+ years, or equivalent practical experience.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
