Senior ASIC Digital Design Engineer

Role Summary

This position is for a highly experienced digital design and verification engineer with expertise in ASIC development and system validation, contributing to the architecture and construction of advanced silicon chips.

Experience Level

Minimum 10 years of relevant professional experience in ASIC design and verification roles, particularly in hardware emulation and system-level validation.

Responsibilities

The selected candidate will be responsible for:

• Design and implementation of digital architectures for high-performance mixed-signal SoCs.
• Development of hardware emulation strategies leveraging FPGA platforms like Zebu and HAPS.
• Validation of system-level prototypes for protocols such as PCIE, Ethernet, and USB.
• Creating verification environments using UVM methodology and developing comprehensive test plans.
• Utilizing advanced scripting techniques in Shell, Perl, Python, and C++ to streamline workflows.
• Collaborating with cross-functional teams to resolve design challenges and ensure timely delivery.
• Performing testing on test-chips and analyzing results for improvement.

Requirements

Candidates should possess:

• Extensive experience with ASIC design, verification, or system validation.
• In-depth knowledge of hardware emulation platforms, specifically Zebu and HAPS.
• Strong background in system-level validation of industry-standard protocols.
• Proficiency in UVM methodology and SystemVerilog.
• Advanced skills in scripting (Shell, Perl, Python, and C++).
• Understanding of digital signal processing and high-speed data recovery circuits.
• Experience in firmware development is considered a plus.

Education Requirements

A degree in Electrical Engineering, Computer Science, or a related field is typically required. Advanced degrees are preferred alongside extensive professional experience.