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Senior ASIC Design Engineer β€” Video Silicon IP

ByteDance
June 23, 2026
Full-time
On-site
San Jose, California, United States
RTL Design Jobs, Level - Senior

Job Title

Senior ASIC Design Engineer β€” Video Silicon IP

Role Summary

Join ByteDance's Video Silicon IP team in San Jose to design and deliver ASIC hardware for video codecs and image processing. The role focuses on front-end RTL design, microarchitecture, and close collaboration with architecture, algorithm, verification, and physical design teams.

Primary mission: implement efficient, low-power, high-performance video processing IPs for multi-standard codecs.

Experience Level

Senior level; the posting requests approximately 5 years of ASIC front-end design experience as a primary RTL owner.

Responsibilities

Key responsibilities include:

  • Design hardware accelerators for video encoding, decoding, and image processing.
  • Develop micro-architectures to meet area, power, and performance targets for multi-standard codec cores.
  • Translate codec standards into implementable hardware architectures with algorithm teams.
  • Implement RTL in SystemVerilog/Verilog or High Level Synthesis (HLS) for codec pipeline stages.
  • Collaborate with verification using UVM/DPI/C++ testbenches; debug RTL and drive coverage closure.
  • Support synthesis, timing analysis, CDC/RDC checks and coordinate with physical design on floorplan and timing closure.
  • Use Python to automate EDA flows and support FPGA prototyping for pre-silicon validation.

Requirements

Must-have:

  • Approximately 5 years of ASIC front-end design experience as primary RTL owner.
  • Proficiency in SystemVerilog RTL design or High Level Synthesis (HLS).
  • Experience with UVM, DPI and C++ for verification.
  • Strong understanding of VLSI design concepts including pipelining, clock gating, and memory architectures.
  • Proficiency in Python for EDA flow automation.

Nice-to-have:

  • Familiarity with video codec standards (H.265/HEVC, H.266/VVC, AV1, VP9, H.264/AVC).
  • Experience with ISP or ML-based image/video compression and FPGA prototyping.
  • Practical experience using LLMs (e.g., GitHub Copilot, Claude, ChatGPT) to assist RTL design workflows.

Education Requirements

M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field (specified in the posting).


About the Company

Company: ByteDance

Headquarters: Beijing, China

ByteDance is a Beijing-based multinational internet technology company known for consumer apps like TikTok and Toutiao. The company develops AI-driven content platforms, advertising products, and research in machine learning, video technologies, and cloud services.

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Date Posted: 2026-06-17