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Senior ASIC Design Engineer, GPU Core Pipeline IP

NVIDIA
September 28, 2026
Full-time
Remote friendly (Bengaluru, Karnataka, India)
Worldwide
RTL Design Jobs, Level - Senior

Job Title

Senior ASIC Design Engineer, GPU Core Pipeline IP

Role Summary

Design and implement control subsystems and RTL for GPU core pipeline IP. Work on micro-architecture, RTL development, and integration with verification and physical design teams to meet performance, power, area, and timing targets.

Experience Level

Senior - typically requires 5+ years of relevant ASIC/RTL design experience.

Responsibilities

Deliver RTL and micro-architecture for GPU IP and collaborate across teams to validate and bring silicon to production:

  • Define micro-architecture and implement RTL for GPU ASIC units or subsystems.
  • Develop RTL using Verilog/SystemVerilog and ensure adherence to performance, power, area, and timing goals.
  • Collaborate with architects, verification, and physical design teams on specifications and implementation tradeoffs.
  • Work with verification engineers to plan and achieve comprehensive validation and coverage.
  • Participate in silicon bring-up, post-silicon debug, and performance analysis.

Requirements

Key technical skills and practical experience required and preferred.

Must-have:

  • Experience in RTL design and micro-architecture development at the unit or subsystem level.
  • Proficiency with Verilog and SystemVerilog for RTL implementation and design intent.
  • Familiarity with C++ and object-oriented programming concepts.
  • Strong understanding of digital design fundamentals: synchronous design, timing, and clock/reset methodologies.
  • Solid understanding of computer architecture concepts and strong analytical/problem-solving skills.
  • Exposure to industry-standard design, simulation, and debug tools and ASIC design methodologies.

Nice-to-have:

  • Prior experience in 3D graphics processing or processor design.
  • Experience with scripting and tool development (Python, Perl) and C programming.
  • Experience with ASIC implementation flows including synthesis, timing closure, DFT, and physical design considerations.
  • Excellent debug skills and effective communication/teamwork abilities.

Education Requirements

B.Tech. or M.Tech. degree in engineering (or equivalent) is stated; role expects 5+ years of relevant experience.


About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

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Date Posted: 2026-09-28