Senior ASIC Design Engineer

Company Overview

SpaceX is focused on developing technologies to facilitate space exploration. The company is actively working on providing advanced broadband internet through its Starlink satellite constellation.

Role Summary

The Senior ASIC Design Engineer will be responsible for developing innovative FPGA and ASIC designs that will be utilized in space and ground systems, contributing to enhancing global connectivity.

Experience Level

This position requires candidates to have at least 5 years of experience in RTL implementation, specifically in ASIC design and verification.

Responsibilities

• Evaluate architectural trade-offs for performance and system limitations.
• Define micro-architecture and implement RTL designs using Verilog/System Verilog.
• Collaborate with verification teams to ensure comprehensive design coverage.
• Provide timing constraints and assist the physical implementation team.
• Engage in silicon bring-up and validation processes.

Requirements

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 5+ years of relevant experience in RTL implementation.
• Ability to address complex design problems and optimize power consumption.
• Experience with ASIC/SoC integration and multicore CPU design.
• Familiarity with bus protocols (e.g., AXI, AHB).
• Proficient in scripting with Python or TCL.
• Knowledge of EDA tools for HDL simulations and FPGA support.
• Adaptable to dynamic project environments while maintaining teamwork.
• Willingness to work extended hours and weekends as necessary.

Education Requirements

Bachelor’s degree in electrical engineering, computer engineering, or computer science is required for this role.