Senior ASIC Design Engineer

Role Summary

NVIDIA is seeking a skilled Senior ASIC Design Engineer to become a member of our Memory Subsystem Team. You will engage with a talented group of engineers to design and implement sophisticated coherent fabrics for Tegra SoCs, contributing significant advancements in areas including consumer graphics, self-driving vehicles, and artificial intelligence.

Experience Level

This position requires a minimum of 5 years of relevant industry experience in ASIC design, particularly with a focus on high-speed coherent interconnects and protocol bridges. A Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience) is essential.

Responsibilities

• Collaborate with cross-functional teams including architects, design verification, formal verification, and physical design to deliver superior solutions.
• Oversee micro-architecture and design aspects, including RTL design, synthesis, and timing analysis utilizing advanced CAD tools.
• Work with complex requirements around area, latency, power, and bandwidth for NVIDIA SOC Interconnects.
• Guide ASIC design flow processes such as emulation, prototyping, DFT, and ATE test development.
• Mentor junior engineers and interns to foster their growth in the field.

Requirements

• MS/Ph.D. in Electrical Engineering, Computer Engineering, or a related discipline.
• Over 5 years of industry experience with a proven background in coherent interconnects and system-level cache.
• Proficiency in Verilog or VHDL and familiarity with scripting languages like PERL.
• Knowledge of industry-specific standards (CHI/CXL/PCI-E) is advantageous.
• Able to navigate multiple clock domains and asynchronous interfaces effectively.
• Excellent communication and interpersonal skills are necessary.

Education Requirements

A degree in Electrical Engineering, Computer Engineering, or a closely related field is required. Advanced degrees (MS/PhD) are preferred.