Job Title
Senior Analog/mixed-signal IC Design Engineer - Acacia (Hybrid)
Role Summary
Hybrid (three days per week in the San Jose, CA office) senior analog/mixed-signal IC design engineer on the Acacia mixed-signal IC design team. Responsible for architecting, designing, laying out, measuring and productizing ultra-deep-submicron CMOS transceiver IC blocks for optical communications (100Gβ1T).
Work focuses on high-speed transceivers used in data center and telecommunication networks and requires close collaboration with digital/DSP, system, packaging and module teams.
Experience Level
Senior-level. See Education Requirements for the employer's specific years-of-experience equivalents.
Responsibilities
Key responsibilities include:
- Architect, design, layout, characterize and productize high-speed analog/mixed-signal CMOS IC blocks for optical transceivers.
- Lead design efforts for large blocks on complex chips; mentor engineers and track deliverables.
- Perform peer reviews, define and enforce design methodology, and drive designs from conception through production.
- Collaborate with digital/DSP, system, packaging and hardware teams to meet signal and power integrity specifications.
- Develop and validate high-speed serializers/deserializers, data converters, PLLs/clocking, analog front-ends, regulators, drivers and equalization circuitry.
Requirements
Must-have skills and experience:
- Proven analog/mixed-signal IC design experience for high-speed communications products in CMOS ultra-deep-submicron processes.
- Hands-on experience with design, simulation and measurement of high-speed ICs across multiple areas such as serial links, data converters, PLLs/clocking, analog front-ends, regulators, or output drivers.
- Experience leading complex IC projects and delivering production-quality silicon (architecture through tapeout and bring-up).
- Practical knowledge of signal and power integrity and experience collaborating with packaging and hardware teams for system-level requirements.
Nice-to-have:
- Experience with FinFET technologies, high-frequency passive components (inductors, transformers, transmission lines), and custom transistor layout.
- Floorplanning experience for mixed-signal chips (power/ground, digital/analog routing) and designing for manufacturability.
- Experience with ESD lab practices and product bring-up.
- Familiarity with Cadence Virtuoso, Spectre/APS/SpectreX, Matlab, EMX and mixed-signal AMS simulation flows.
Education Requirements
BSEE with 12+ years, or MS with 8+ years, or PhD with 5+ years of relevant experience β or equivalent practical experience. Fields: electrical engineering or closely related technical disciplines. (This reflects the employer's stated degree and years-equivalent guidance.)
About the Company
Company: Cisco Systems
Headquarters: San Jose, CA, United States
Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).

Date Posted: 2026-08-17