Scientist — ASIC Verification, Interface IP (PCIe / CXL)
SynopsysJob Title
Scientist — ASIC Verification, Interface IP (PCIe / CXL)
Role Summary
Lead verification architect responsible for defining and owning RTL verification strategy and scalable UVM testbench architectures for Interface IP controllers (PCIe, CXL, UCIe) at block and chip-integration levels.
Work with design, architecture, product, and global teams to map protocol specifications into verification plans, debug complex protocol interactions, and mentor verification engineers to raise team capability.
Experience Level
Senior — requires extensive experience; posting specifies 20+ years of hands-on ASIC RTL verification experience.
Responsibilities
Primary responsibilities include building testbenches, defining verification strategy, debugging, and mentoring.
- Define and architect RTL verification strategies for Interface IP controllers (PCIe, CXL, UCIe) at block and chip-integration levels.
- Design and own scalable UVM testbench architectures and advanced verification methodologies across protocol variants and product generations.
- Develop verification plans that map protocol specs to coverage models, corner cases, and system interactions.
- Debug complex protocol interactions and root-cause issues across RTL, testbench, and tools.
- Collaborate with design, architecture, product, and cross-regional teams to align verification with roadmaps and customer requirements.
- Mentor and review work of verification engineers, establish best practices, and lead technical discussions.
Requirements
Must-have technical skills and experience.
- 20+ years of hands-on ASIC RTL verification experience and a proven record of shipping complex digital designs.
- Deep protocol expertise in PCIe (Gen3–Gen6), CXL (1.x, 2.0, 3.0), or UCIe, including link training, error handling, and system-level interactions.
- Strong experience with SystemVerilog, UVM, and constrained-random verification.
- Expertise in verification planning, coverage modeling, assertion-based verification, and familiarity with formal methods.
- Experience operating at an architect or technical lead level with minimal oversight; strong mentoring and cross-functional leadership skills.
- Excellent written and verbal communication skills for explaining verification tradeoffs to architects, designers, and product managers.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
