RTL Synthesis Digital Design Sr. Engineer
SynopsysJob Title
RTL Synthesis Digital Design Sr. Engineer
Role Summary
The Sr. Engineer will architect and develop RTL for high bandwidth PHY IP and test chips. This role involves collaboration with cross-functional teams to resolve technical challenges and mentor junior engineers while driving innovations in chip design and IP integration.
Experience Level
Senior level, with 2 to 6+ years of experience in RTL design and synthesis.
Responsibilities
The main responsibilities include:
- Architecting and developing RTL for high bandwidth PHY IP and test chips.
- Defining synthesis constraints and resolving STA and simulation issues.
- Collaborating with verification, controller, and lab teams.
- Performing logical and physical synthesis, formal verification, and quality checks.
- Analyzing timing violations and generating reports.
- Mentoring junior engineers and supporting digital flow development.
Requirements
Key qualifications include:
- BS/MS/PhD in Electronics Engineering or related field.
- 2 to 6+ years RTL design and synthesis experience.
- Expertise in industry tools (VCS, Verdi, Spyglass, Synopsys sign-off).
- Strong scripting skills (Perl, TCL, Python, Shell).
- Good English communication skills.
Education Requirements
BS/MS/PhD in Electronics Engineering or related field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
