RTL / SoC Design Integration Lead

Role Summary

The RTL / SoC Design Integration Lead will be part of the AECG ASIC organization, responsible for providing hands-on technical leadership in developing microarchitecture, implementing RTL designs, and ensuring quality through design checks and verification reviews for next-generation ASICs.

Experience Level

This position is suitable for professionals with over 8 years of experience in an ASIC RTL Design execution role, demonstrating deep understanding of end-to-end development processes, SoC architecture, and processor systems.

Responsibilities

• Define and specify micro-architecture of ASIC building blocks based on architecture, PPA, DFT, and Functional Safety requirements.
• Design and debug complex blocks in Verilog / System Verilog.
• Analyze design metrics to optimize PPA and conduct RTL Integration.
• Collaborate with implementation, verification, and physical design teams to ensure high-quality designs and successful tape-outs.
• Address customer challenges through enhancements to product architecture and micro-architecture.
• Lead teams for RTL design in collaboration with cross-functional teams.

Requirements

• Strong analytical and problem-solving skills.
• Good communication skills, both written and verbal.
• Expertise in ASIC design flow and experience with RTL design.
• Knowledge of CPU, AXI Interconnect, and I/O peripherals.
• Familiarity with ASIC design tools and scripting languages like TCL, Perl, and Python.
• Proficiency in using version control systems like Git.
• Experience in low power digital design and analysis.

Education Requirements

A BE, B.Tech, BS, ME, MTech, or MS degree in Electronics, Electrical, or Computer Engineering is required. Hands-on experience in design and integration of complex subsystems or SoC level integration is preferred.