RTL Design & Verification - Senior Staff Engineer
SynopsysRole Summary
The role involves RTL design and verification with responsibilities focused on ASIC digital design. The position is based in Yerevan, Armenia.
Experience Level
Senior level position.
Responsibilities
Key responsibilities include:
- Design and verify RTL for ASIC projects.
- Work collaboratively with other engineering teams.
- Ensure design meets specified standards and requirements.
- Lead verification activities and mentor junior engineers.
Requirements
Must-have qualifications include:
- Extensive experience in RTL design and verification.
- Strong background in digital design and ASIC methodologies.
- Experience with verification tools and languages.
- Ability to work in a team-oriented environment.
Education Requirements
Information not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
