RTL Design & Verification Engineer (R&D Engineering, Sr Engineer)

Job Title

RTL Design & Verification Engineer (R&D Engineering, Sr Engineer)

Role Summary

The RTL Design & Verification Engineer at Synopsys is responsible for developing and verifying complex digital designs in a fast-paced R&D environment. This role requires a deep understanding of RTL design and verification processes to ensure high-quality outputs in our projects.

Experience Level

Senior

Responsibilities

• Design and implement complex RTL blocks.
• Develop and execute verification plans.
• Perform RTL simulations and debug issues as they arise.
• Collaborate with cross-functional teams to ensure designs meet specifications.
• Optimize designs for performance and power efficiency.

Requirements

• Bachelor's or Master’s degree in Electrical Engineering or related field.
• 5+ years of experience in RTL design and verification.
• Proficient in SystemVerilog and UVM.
• Strong problem-solving skills and attention to detail.
• Ability to work effectively in a team-oriented environment.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering or related field.