RTL Design Staff Engineer

Role Summary

The RTL Design Staff Engineer will develop RTL specifications and architectures for High Bandwidth Interface PHY IP. This role requires a strong background in electronics or telecommunications along with collaboration in cross-functional teams.

Experience Level

Senior; 5+ years of experience in ASIC or PHY IP development.

Responsibilities

The responsibilities include:

• Develop RTL specifications and architectures for High Bandwidth Interface PHY IP.
• Define synthesis constraints and resolve STA and gate-level simulation issues.
• Collaborate with verification, controller, and lab teams for design and debugging.
• Support RTL to GDS flow during logic implementation.
• Lead projects and train junior engineers.
• Work with customers to resolve technical RTL issues.

Requirements

The following are required:

• BS/MS/PhD in Electronics Engineering or Telecommunications.
• 5+ years of RTL design experience for ASIC or PHY IP.
• Expertise in VCS, Verdi, Spyglass, and scripting (Perl, TCL, Python).
• Knowledge of clock domain crossing, APB, JTAG protocols.
• Strong English communication skills.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.