RTL Design Sr. Staff Engineer
SynopsysJob Title
RTL Design Sr. Staff Engineer
Role Summary
The RTL Design Sr. Staff Engineer is responsible for designing and verifying DDRPHY/LPDDRR/HBM test chips. This role involves collaborating with cross-functional teams and ensuring robust memory interface solutions.
Experience Level
Senior level, requiring 6+ years of experience in RTL design and verification.
Responsibilities
Key responsibilities include:
- Designing and verifying DDRPHY/LPDDRR/HBM test chips using SystemVerilog/Verilog.
- Collaborating with analog and mixed-signal teams.
- Automating workflows using scripting languages.
- Debugging complex hardware issues in lab validation.
- Documenting specifications and processes.
- Driving improvements in design, DFT, and DFM flows.
Requirements
Must-have skills include:
- 6+ years in RTL design/verification (SystemVerilog/Verilog).
- Experience with high-speed interfaces (e.g., DDR/HBM preferred).
- Proficiency in scripting (Python, Perl, Tcl, Shell).
- Solid knowledge of ASIC/IP flows and DFT/DFM.
- Experience debugging complex hardware issues.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
