RTL Design Lead for IP Subsystems

Role Summary

The RTL Design Lead for IP Subsystems at Advanced Micro Devices will be responsible for leading a front-end design and integration team focused on cutting-edge technology. This role requires collaboration with architecture, IP design, and physical design teams to ensure successful silicon execution.

Experience Level

This position is targeted at candidates with 12-15 years of full-time experience in IP hardware design, offering an opportunity for seasoned professionals to take on leadership responsibilities.

Responsibilities

The key responsibilities include:

• Designing IP and subsystems with integration of AMD and third-party IPs.
• Performing quality checks (lint, CDC, and power rule checks) on power-gated digital designs.
• Collaborating with the IP team to support design verification, implementation, and delivery to SoC.
• Working with SOC teams to ensure the completeness of the IP at the SOC level, including aspects like connectivity and DFT.

Requirements

Candidates must meet the following requirements:

• Proficiency in Verilog/System Verilog for high-speed, multi-clock digital designs.
• Familiarity with Verilog lint tools (Spyglass) and simulation tools (VCS).
• Knowledge of clock domain crossing (CDC) tools and SoC design flows.
• Understanding of power management techniques like Power Gating and Clock Gating.
• Experience with embedded processors and data fabric architectures (NoC).
• Strong written and verbal communication skills.
• Able to work across various geographical functional teams.
• Effective problem-solving and analytical abilities.

Education Requirements

A Bachelor's degree in Computer Engineering or Electrical Engineering plus 15 years of full-time experience in IP hardware design, or a Master’s degree with 12 years of relevant experience is required.