RTL Design Engineer

Job Title

RTL Design Engineer

Role Summary

Senior RTL engineer responsible for designing and delivering digital IP and top-level RTL from specifications, supporting integration into SoCs, and collaborating with verification and physical design teams. The role covers architecture, RTL coding, linting and static checks, low-power implementation, and debug.

Experience Level

Senior — minimum 10 years of experience in digital RTL design (Verilog/SystemVerilog).

Responsibilities

Key responsibilities include implementing RTL from requirements, ensuring quality and integration readiness, and supporting verification and physical design closure.

• Develop micro-architecture and translate specifications into RTL/IP.
• Write and maintain RTL (Verilog/SystemVerilog; VHDL experience useful) for IP development and integration.
• Design top-level RTL, integrate blocks, manage clocks, resets and configuration registers.
• Perform linting, CDC analysis, synthesis checks, LEC and STA; use tools such as Spyglass.
• Ensure synthesizability, timing quality and low-power implementation (UPF/CPF).
• Support verification team with debug and triage of functional issues.
• Support physical design teams on timing constraints and timing closure topics.
• Take ownership of tasks and drive deliverables to closure.

Requirements

Must-have technical skills and experience; followed by desirable skills.

• Must-have:
  • 10+ years of RTL design experience using Verilog/SystemVerilog.
  • Experience developing micro-architecture from requirement documents and designing from scratch.
  • Experience applying linting, CDC checks and other quality controls; debugging functional breaks.
  • Familiarity with synthesis flows, LEC, STA and timing-quality analysis.
  • Experience with low-power design implementation (UPF/CPF) and related flows.
  • Experience supporting SoC integration and collaborating with verification and physical design teams.
  • Strong communication and collaboration skills; ownership mindset.
• Nice-to-have:
  • Experience with DMA, memory controller design, MIPI DSI/CSI, data/control pipelines, interconnects and AMBA interfaces.
  • Design/verification experience with JESD204C and licensed 3rd-party IP/PHY.
  • Scripting or design-automation experience (Python).
  • DFT awareness and experience addressing DFT-related functional issues.
  • VHDL experience.

Education Requirements

Not specified.

About the Company

Company: Glow Networks

Provides ASIC and RTL design services for semiconductor and SoC projects, including RTL/IP development, integration, low-power design (UPF/CPF), lint/CDC checks, verification support, and collaboration with physical design teams.