RTL Design Engineer

Job Title

RTL Design Engineer

Role Summary

Contract position to design and verify digital RTL components for advanced ASIC/SoC projects. The role involves implementing RTL, building and running verification environments, and collaborating with architecture, verification, and implementation teams.

Work focuses on RTL development, simulation-based verification, and debugging across synthesis, timing, CDC, and DFT-aware flows. Use of AI-assisted design and verification tools is expected.

Experience Level

Mid-level. Years of experience not specified.

Responsibilities

Primary responsibilities include RTL design, verification, and cross-functional collaboration.

• Design and develop digital RTL components for chip design workflows.
• Create and maintain testbenches, simulation environments, and verification infrastructure using SystemVerilog and UVM.
• Perform design verification and debug RTL issues using simulation logs and waveform tools.
• Work across ASIC design flows including synthesis, static timing analysis, CDC, and DFT-aware design.
• Collaborate with architecture, verification, and implementation teams to clarify specifications and resolve issues.
• Document design specifications, verification plans, and technical trade-offs.
• Leverage AI-assisted tools to improve design, verification, and debugging efficiency.

Requirements

Must-have technical skills and experience are listed below. Nice-to-have items follow.

• Must-have: Strong experience in RTL design or design verification engineering.
• Must-have: Proficiency in Verilog and SystemVerilog; practical experience with UVM methodologies.
• Must-have: Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, and bus protocols.
• Must-have: Experience with ASIC design and verification flows, including synthesis, timing analysis, CDC, and coverage analysis.
• Must-have: Familiarity with EDA tools for simulation, debugging, and verification; ability to debug complex RTL and verification issues.
• Must-have: Strong communication and collaboration skills across engineering teams.
• Nice-to-have: Experience with AMBA protocols (AXI, AHB, APB).
• Nice-to-have: Background in CPU, GPU, ML accelerators, networking, or SoC design.
• Nice-to-have: Familiarity with formal verification or coverage-driven verification methodologies.

Education Requirements

Not specified.

About the Company

Company: CodeGeniusRecruit

Recruiting/staffing firm focused on technology and engineering roles, matching candidates with employers for remote, contract, and full-time positions.