RTL Design Engineer

Job Title

RTL Design Engineer

Role Summary

Design RTL and microarchitecture for SoC subsystems and IP in connectivity networking products, working across the full semiconductor development cycle from specification through tapeout.

Collaborate with verification, physical design, software and FPGA teams to meet area, power and performance targets for next-generation SoC designs.

Experience Level

Senior-level role. Typical candidates have multiple years of ASIC/SoC RTL design experience (see Education Requirements for the employer's stated years); equivalent practical experience will be considered.

Responsibilities

Primary responsibilities include implementing, documenting and delivering high-quality RTL for SoC blocks and subsystems, and supporting integration and tapeout activities.

• Microarchitecture and RTL design of SoC subsystems/IP (Verilog/VHDL)
• Perform RTL quality checks (lint, CDC, LEC) and ensure code/functional coverage goals
• Create and maintain microarchitecture and hardware block documentation
• Analyze, debug and fix issues reported by verification teams
• Develop synthesis constraints for blocks and subsystems
• Work with SOC architects and leads on integration, verification plans, DFT and physical design sign-off
• Support physical design, verification, software and FPGA teams to achieve successful tapeout

Requirements

Must-have skills and experience required to perform the role.

Must-have:

• Proven multi-project RTL SoC design experience using Verilog or VHDL
• ASIC/FPGA debug methodologies and practical debug experience
• Experience with synthesis (Design Compiler) and formal verification (LEC)
• Strong understanding of timing closure and timing-driven design
• Familiarity with lint and CDC flows and interpreting coverage metrics
• Ability to produce clear microarchitecture and hardware documentation
• Effective cross-functional collaboration and communication skills

Nice-to-have:

• Experience with SerDes PHY, DSP or analog mixed-signal blocks
• Knowledge of Ethernet, PCIe and other high-speed interfaces
• Familiarity with bus protocols and peripherals (AHB, AXI, PCIe, USB, etc.)
• Architecture and micro-architecture development experience

Education Requirements

Employer states: Bachelor's degree in Science, Engineering or related field with 8+ years of relevant ASIC/RTL design/verification/integration experience; OR Master's degree in Science, Engineering or related field with 7+ years; OR PhD in Science, Engineering or related field with 6+ years. Equivalent practical experience will be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.