RTL Design and Verification R&D Engineering Staff Engineer

Job Title

RTL Design and Verification R&D Engineering Staff Engineer

Role Summary

We are seeking an experienced RTL Design and Verification Engineer to contribute to the development and verification of advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects.

Experience Level

Level - Senior

Responsibilities

• Designing and verifying RTL for advanced SLM IPs and next-generation 3D-IC projects.
• Developing comprehensive test cases for robust product functionality and performance.
• Collaborating with customers and internal engineering teams to resolve technical issues, involving hands-on debugging and root cause analysis.
• Staying current with emerging trends and best practices in SLM and 3D-IC technologies.
• Improving verification methodologies and automation flows.
• Documenting design specifications and verification plans to ensure transparency and repeatability.
• Participating in code reviews and technical discussions to drive innovation and continuous improvement.

Requirements

• BS/MS in Computer Science, Electrical Engineering, or related field.
• 5+ years of hands-on experience in RTL design and verification.
• Proficiency in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies.
• Experience in Unix/Linux environments.
• Strong debugging and problem-solving skills in complex chip design environments.
• Excellent communication skills in English.
• Knowledge of digital, analog, and mixed-signal IP/circuit design is a plus.
• Familiarity with 3D-IC standards and semiconductor verification best practices is desirable.

Education Requirements

BS/MS in Computer Science, Electrical Engineering, or related field.