RTL Design and Verification Engineer - R&D Engineering Sr. Engineer

Role Summary

As an RTL Design and Verification Engineer, you will be responsible for designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, particularly in next-generation 3D-IC projects. Your role requires hands-on experience in creating comprehensive test cases, debugging, and collaboration with both internal teams and clients to resolve technical issues.

Experience Level

5 years of hands-on experience in RTL design and verification.

Responsibilities

• Designing and verifying RTL for SLM IPs.
• Developing test cases for robust product functionality and performance.
• Collaborating with engineering teams to resolve technical issues.
• Keeping updated with trends in SLM and 3D-IC technologies.
• Improving verification methodologies and automation flows.
• Documenting design specifications and verification plans.
• Participating in code reviews to drive innovation.

Requirements

• BS/MS in Computer Science, Electrical Engineering, or related field.
• 5 years of hands-on experience in RTL design and verification.
• Proficiency in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies.
• Experience in Unix/Linux environments.
• Strong problem-solving skills in complex chip design.
• Excellent written and verbal communication in English.
• Knowledge of digital, analog, and mixed-signal IP/circuit design is a plus.
• Familiarity with 3D-IC standards and semiconductor verification practices is desirable.

Education Requirements

BS/MS in Computer Science, Electrical Engineering, or related field.