Role Summary
The R&D Engineering Sr. Engineer will work in the Emulation Transactor Development Team, focusing on developing and deploying emulation models for advanced computing systems, particularly in emulation mode development for Zebu.
Experience Level
Senior, with 5+ years of relevant experience.
Responsibilities
The successful candidate will be responsible for:
- Developing and deploying emulation models for Zebu, focusing on bus protocols such as PCIe, USB, CSI, and DSI.
- Implementing designs in C++, RTL, and SystemVerilog-DPIs.
- Collaborating with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments.
- Creating and optimizing use models and applications for various emulation projects.
- Conducting thorough verification processes to ensure the highest quality of emulation models.
- Providing technical guidance and mentorship to junior team members.
Requirements
Must-have skills include:
- Strong programming skills in C++ and knowledge of object-oriented programming concepts.
- 5+ years of experience in the relevant domain.
- Proficiency in HDL languages, particularly System Verilog and Verilog.
- Familiarity with digital design concepts and verification methodologies.
- Experience with scripting languages like Perl or TCL is a plus.
- Knowledge of protocols such as ENET, HDMI, MIPI, AMBA, and UART is advantageous.
Education Requirements
Education requirements not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

Date Posted: 2026-03-16