R&D Engineering, Sr Engineer (C++, RTL, Verilog)
SynopsysJob Title
R&D Engineering, Sr Engineer (C++, RTL, Verilog)
Role Summary
This role is focused on R&D engineering, primarily involving the use of C++, RTL, and Verilog in various projects. The engineer will work within a team dedicated to advancing engineering practices and methodologies.
Experience Level
Senior-level (exact years of experience not specified).
Responsibilities
Key responsibilities include:
- Developing and implementing software solutions in C++.
- Working with RTL and Verilog for various projects.
- Collaborating with a team of engineers to drive innovation.
Requirements
Must-have skills and qualifications include:
- Proficiency in C++ programming.
- Experience with RTL and Verilog.
- Strong problem-solving skills and ability to work collaboratively.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
