R&D Engineering Sign-Off Principal Engineer

Role Summary

As a member of the IP Digital Design Methodology team, you will work with global teams to define ASIC design standards and assist IP development teams. Involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.

Experience Level

10+ years of hands-on experience in ASIC Digital Signoff Engineering.

Responsibilities

• Develop and deploy advanced node signoff methodologies for IP designs targeting different foundries.
• Collaborate with teams to drive industry best PPA for IP designs.
• Evaluate aspects of the development flow including signoff timing, power, physical verification, EM/IR analysis, and ECOs.
• Develop and maintain digital design methodologies including documentation, scripts, and training materials.
• Act as a liaison between EDAG tool and IP design teams.
• Continuously improve design processes for efficiency and performance.

Requirements

• BS or MS in Electrical Engineering.
• Deep understanding of high-speed digital IP cores and/or SOCs development.
• Experience with EM and IR flows.
• Strong problem-solving and debugging skills.
• Solid written and verbal communication skills.
• Familiarity with Synopsys tools (StarRC, ICV) and protocols (HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, DDR) is a plus.

Education Requirements

BS or MS in Electrical Engineering.