R&D Engineering Senior Staff

Date Posted: 02/23/2026

Company Overview: Synopsys is a leader in chip design, verification, and software content creation, driving innovations that shape the way we live and connect.

Role Summary

The R&D Engineering Senior Staff focuses on refining hardware verification through innovative partitioning solutions. Candidates are expected to utilize their expertise in hardware design and verification methodologies to enhance chip performance and integration efficiency.

Experience Level

This role requires a minimum of 6 years of relevant hands-on experience in hardware partitioning, emulation, or hardware-assisted verification, preferably with advanced academic credentials such as a Master’s degree.

Responsibilities

• Design and optimize hardware partitioning algorithms for hardware-assisted verification frameworks.
• Collaborate with teams to implement effective partitioning methodologies.
• Analyze RTL designs to propose optimal partitioning strategies and address co-verification issues.
• Drive integration of these solutions within Synopsys' verification tools.
• Mentor junior engineers and lead technical discussions.
• Stay updated on industry advancements and contribute to research in partitioning technology.
• Engage with clients to align product features with their challenges.

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, or similar field.
• 6+ years experience in hardware verification techniques.
• Proficient in RTL design (Verilog, SystemVerilog, VHDL) and logic synthesis.
• Deep knowledge of partitioning algorithms and hardware-software co-verification issues.
• Experience with emulation platforms and EDA tools.
• History of deploying scalable verification solutions in production environments.

Education Requirements

Candidate must possess a Master’s or advanced degree in a relevant discipline such as Electrical Engineering or Computer Engineering.