R&D Engineering Senior Manager

Role Overview

This position involves leadership and management of teams focused on ASIC design standards and flows within the IP Digital Design Methodology group at Synopsys. This is an on-site role located in either Boston or Toronto and emphasizes cutting-edge technology development.

Position Summary

The R&D Engineering Senior Manager will oversee the ASIC design processes, ensuring that innovative techniques are applied for creating high-performance digital IP cores. This candidate will play a crucial role in setting industry standards and methodologies in collaboration with global engineering teams.

Experience Level

Candidates should possess over 10 years of relevant experience in ASIC digital implementation, including a minimum of 2-3 years in a managerial capacity. A strong background in tackling high-speed digital technology challenges is essential.

Key Responsibilities

• Lead and mentor teams to achieve optimal power, performance, and area (PPA) in IP designs.
• Develop comprehensive methodologies for design implementation from RTL to GDSII.
• Evaluate design flows such as test logic, synthesis, and power analysis.
• Create documentation, training materials, and facilitate communication between teams.
• Drive continuous process improvements to enhance efficiency in design and verification.

Essential Requirements

• Bachelor’s or Master’s degree in Electrical Engineering.
• Direct experience with design tools (Fusion Compiler or similar).
• Understanding of ASIC design flows and physical design.
• Proficient in fostering collaboration across different teams.
• Strong problem-solving and communication skills.
• Experience with Synopsys tools and high-speed protocols like PCIe, HDMI, and DDR is advantageous.

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering (or a related field) is required to qualify for this position.