R&D Engineer IC Design 4

Role Summary

The R&D Engineer IC Design 4 is responsible for front-end design and verification of design blocks for ASIC cores. The role involves architecture definition, logic design, synthesis, constraint development, design verification through simulation, formal verification, and timing analysis from the physical implementation.

Experience Level

Senior; requires 6+ years of experience with a Master's degree or 8+ years with a Bachelor's degree in ASIC design/implementation.

Responsibilities

The responsibilities of this role include:

• Design logic blocks based on systems requirements documents.
• Simulate and debug designs with Verilog simulation.
• Develop architecture definition and perform logic design.
• Conduct synthesis and constraint development.
• Perform design verification through simulation and formal verification.
• Analyze timing from physical implementation.
• Collaborate effectively as part of a large team across multiple geographies.

Requirements

Must-have skills and experiences:

• Proficiency in TCL/Perl scripting.
• Experience with Synopsys Design Compiler/DC topo or Cadence RTL compiler for synthesis.
• Timing analysis experience with Primetime.
• Understanding of LIB models for timing.
• Familiarity with formal verification tools such as Synopsys Formality or Cadence Conformal.
• Experience with Spyglass Lint.
• Power analysis experience of RTL and gate level netlists.
• Understanding of DFT and scan methodology.
• Version control experience (svn, git, etc).

Education Requirements

BS/MS in Electrical or Computer Engineering or equivalent is required.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.