Principal Verification Engineer

Job Title

Principal Verification Engineer

Role Summary

Rambus is a global chip and silicon IP provider, seeking a Principal Verification Engineer to join the Memory Interface chips team in Bangalore. This role focuses on the verification of DDR, from understanding design to sign-off and post-tapeout support.

Experience Level

10+ years of relevant experience in verification engineering.

Responsibilities

• Understand product requirements from specifications and beyond.
• Plan and execute to meet verification sign-off criteria.
• Develop test plans, tests, and verification infrastructure for complex Block level/IP/Sub-system using UVM methodology.
• Guide and mentor the team to meet sign-off requirements.
• Collaborate with architects, designers, and post-silicon teams.

Requirements

• Bachelor's or Master's degree in Electronics.
• Expertise in System Verilog and UVM.
• Strong debugging skills.
• Experience in all verification aspects from design requirements to sign-off.
• Ability to create testbench architectures and build verification setups from scratch.
• Strong verbal and written communication skills.
• Knowledge of I2C/I3C Protocol and DDR3/4/5 memory protocols is preferable.

Education Requirements

Bachelor's or Master's degree in Electronics.