Principal STA Engineer

Job Title

Principal STA Engineer

Role Summary

Technical authority for signoff timing convergence within the Physical Design organization. Responsible for defining and driving shift-left signoff strategies, owning SoC-level static timing analysis (STA) signoff, and ensuring predictable, high-quality SoC closure.

The role requires cross-team collaboration with SoC development, IP, and process groups to align constraints, optimization, and timing analysis.

Experience Level

Senior level. The posting specifies 16+ years of hands-on STA experience and extensive SoC signoff responsibility.

Responsibilities

Core responsibilities include STA signoff, timing optimization, and automation to enable predictable silicon delivery.

• Own SoC-level signoff STA, including timing ECO delivery and GLS enablement.
• Drive co-optimization strategies to meet PPAS (power, performance, area, and cost) targets.
• Develop and maintain PPAS and status dashboards for visibility into timing closure.
• Collaborate with SoC development teams for design convergence and consistent signoff across IP and blocks.
• Rationalize timing margins and provide guidance on signoff and SSTA analysis.
• Analyze design metrics and collateral to propose data-driven process and flow improvements.
• Apply reuse methodologies for IP, libraries, and flows to accelerate execution and consistency.
• Automate and enhance STA flows using TCL, Python, or Perl to improve productivity and repeatability.
• Perform duties in a safe, responsible manner and support Environmental, Health, Safety & Security (EHSS) programs.

Requirements

Must-have skills and experience required for immediate contribution; preferred items listed separately.

• Extensive hands-on STA experience, including SoC-level MCMM STA and physically aware ECO generation.
• Proven ability to define, implement, and mature STA tools, methodologies, and shift-left signoff approaches from a blank slate.
• Experience with timing margin definition, ownership of SoC STA/SSTA signoff, and spice circuit-level timing analysis.
• Familiarity with advanced process nodes, DFT timing modes and analysis, and IP integration challenges.
• Strong scripting and automation skills (TCL, Python, Perl) for flow automation and debugging.
• Analytical mindset with strong communication and cross-team collaboration abilities.

Nice-to-have:

• Experience delivering custom silicon for automotive, HPC, or AI applications.
• Proactive adoption of new tools, flows, and design-reuse best practices; highly detail-oriented and quality-focused.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field (as stated in the posting).

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.