Principal SoC Signoff Engineer

Job Title

Principal SoC Signoff Engineer

Role Summary

Lead development and signoff of timing constraints and static timing analysis (STA) methodologies for complex SoCs and associated digital, AMS, and SerDes IP. Work across specification, RTL, implementation, verification, and EDA partners to define margining, MV/DVFS signoff processes, and shift-left STA flows.

Provide technical leadership and mentorship to engineering teams while driving deployment of AI/ML-enabled STA methods and signoff infrastructure.

Experience Level

Senior level. Requires extensive industry experience (posting specifies 12+ years with detailed experience breakdown).

Responsibilities

Deliver and own STA constraint and signoff work for SoC projects; mentor engineers and coordinate across stakeholders.

• Lead all phases of timing-constraint development for full-chip and sub-chip designs, including digital, AMS, and SerDes IP.
• Define and establish signoff margins and signoff processes from specification through production.
• Develop MV/DVFS (multi-voltage / dynamic voltage and frequency scaling) STA signoff methodologies and UPF/SDC workflows.
• Create and deploy shift-left STA methodologies and mode-reduction strategies to improve signoff predictability.
• Drive adoption of AI/ML-enabled STA techniques in collaboration with EDA partners and internal teams.
• Provide technical mentorship and leadership to engineers, including recent graduates.
• Conduct timing-signoff reviews and establish signoff infrastructure and margining practices for production SoCs.
• Perform all duties in compliance with Environmental, Health, Safety, and Security requirements.

Requirements

Must-have skills and experience:

• 12+ years industry experience, including significant hands-on STA and constraint work (posting specifies breakdown: ≥2 years subsystem RTL, ≥6 years STA constraint development, ≥4 years STA signoff).
• Deep, hands-on expertise developing functional- and test-mode constraints for digital, analog, mixed-signal, and source-synchronous interfaces.
• Proven STA signoff experience, including margining, mode reduction, and methodology infrastructure development.
• Expertise with MV/DVFS designs and advanced proficiency in UPF and SDC.
• Strong proficiency with leading EDA tools (Synopsys, Cadence, or Siemens EDA).
• Excellent leadership, mentoring, communication, analytical, and problem-solving skills.

Nice-to-have:

• Proven track record delivering custom silicon across multiple application domains.
• Experience with Synopsys tool suite and exposure to agentic AI technologies or AI-driven EDA workflows.
• Demonstrated ability to scale and mentor high-performing teams and adopt industry best practices.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field (as stated in the posting).

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.